Ministry of Electronics and IT (MietY), Government of India, have sanctioned a project titled “The Design, Fabrication and Development of Silicon Proven IP Core for High Resolution ADPLL,” under Chip to Start-up (C2S) programme, with the worth of Rs. 2 Crore. The CBIT will be collaborating with OUCE, which is the lead institution in implementing the project. The project involves design and development of full custom ADPLL-IP core and taping out of the same from fabrication labs like SCL-Chandigarh and TSMC. BITSILICA Pvt. Ltd. will be the End User, to commercialize the developed IP. The projects aim is to build highly skilled workforce apart from providing the institutes and start-up, a means for fabricating novel Semiconductor Intellectual properties. The students at various levels will also be benefited by gaining a practical and industrial exposure, working on different stages of IC-Design like simulation, verification, layout, characterization, modelling, etc. The principal of CBIT, Dr. P. Ravinder Reddy has congratulated Mohd Ziauddin Jahangir, Chief Investigator and Dr. D. Krishna Reddy, Co-Chief Investigator of the Project for their exceptional achievements. He has also congratulated other resource persons involved in the project Dr. M. Ramana Reddy and M. Banuchander. With this achievement, CBIT has joined the list of elite institutions with industry level, state of the art projects on fabrication of VLSI Chips.